In recent years, there has been developed a memory matrix utilizing the non-volatile resettable characteristic of a memory semiconductor material like those disclosed in U.S. Pat. No. 3,271,591, granted on Sept. 6, 1966 to S. R. Ovshinsky. Such a memory matrix has been integrated onto a silicon semiconductor substrate as disclosed in U.S. Pat. No. 3,699,543, granted Oct. 17, 1972 to Ronald G. Neale. As disclosed in this patent, the entire matrix, other than the read and/or write circuits, is formed within and on a semiconductor substrate, such as a silicon chip, which is doped to form spaced, parallel X or Y axis conductor-forming regions within the body. In "read-write" memory matrices, the substrate is further doped to form isolating diodes or transistor elements for each active cross-over point. The diode or transistor elements have one or more terminals exposed through openings in an outer insulating coating on the substrate. The other Y or X-axis conductors of the matrix are formed by spaced parallel bands of conductive material deposited on the insulation covered semiconductor substrate. The memory matrix further includes a deposited memory device including a film of said memory semiconductor material on the substrate adjacent each active crossover point of the matrix. The film of memory semiconductor material is connected between the associated Y or X-axis band of conductive material in series with the isolating diode or transistor where such an isolating element is present.
The deposited film memory device used in the memory matrix referred to is a two-terminal bistable device including a layer of memory amorphous semiconductor material which is capable of being triggered (set) into a stable low resistance condition when a voltage applied to the spaced portions of this layer exceeds a given threshold voltage and current is allowed to flow for a sufficient duration (e.g. 1-100 milliseconds or more) to cause after termination thereof, by the slow cooling of the resulting bulk heated film, alteration of the portion of the film through which the current flows to a low resistance crystalline or more ordered condition. This condition remains indefinitely, even when the applied voltage and current are removed, until reset to a high resistance condition as by feeding a high current short duration reset current pulse therethrough (e.g. a 150 ma pulse of 10 microseconds). It has been shown that the set current pulse flows only through a small filament of generally under 5-10 microns which is the only portion of the amorphous film converted to a more ordered or crystalline state of low resistance. The rest of the body of memory semiconductor material remains in its initial high resistance amorphous state.
A readout operation on the voltage memory matrix to determine whether a memory device at a selected cross-over point is in a low or high resistance condition involves the feeding of a voltage below the threshold voltage value across the associated X and Y-axis conductors which is insufficient to trigger the memory switch device involved when in a high resistance condition to a low resistance condition and of a polarity to cause current flow in the low impedance direction of the associated isolating element, and detecting the resulting current or voltage condition.
Manifestly, the reliability of memory matrices in which information is stored in computers and the like is of exceeding importance and some marketing limitations have been heretofore experienced because of the threshold reduction of the device in some cases within a relatively few number of cycles of operation of the matrices and in other cases after prolonged use thereof. I discovered that the short term failure of many of these matrices was due to damage to the memory devices at the usually refractory metal electrodes which electrically connected the memory semiconductor material to the X or Y-axis conductors deposited on top of the memory semiconductor films at the cross-over points of the matrix. These X or Y-axis conductors were commonly deposits of aluminum and the electrodes which interface the aluminum conductors with the memory semiconductor material were usually amorphous molybdenum films which, among other things, prevented migration of the aluminum into the memory semiconductor material when the voltage applied to the deposited film X or Y-axis conductors was positive relative to the X or Y-axis conductors integrated into the silicon chip substrate.
It was discovered that with many repeated set-reset cycles, the threshold voltage characteristics of the memory devices progressively degrades. For example, where the thickness of the memory semiconductor film provided a threshold voltage of 14 volts at room temperature (25.degree.C) when the matrix was initially fabricated and subjected to the usual testing where the memory device undergo about twenty to thirty set-reset cycles, upon the subsequent application of hundreds or thousands of additional set cycles, the threshold voltage value can progressively decrease to a point at or below 8 volts. This threshold degradation poses a serious problem when the read voltage exceeds a degraded threshold voltage value, because then the read voltage will set all unset memory devices to which it is applied and thereby destroy the binary information stored in the matrix involved. A typical read-out voltage used with matrices made by Energy Conversion Devices, Inc., the assignee of the present invention, is in the neighborhood of 5 volts, and the set voltage used therewith is in the neighborhood of 25 volts. At first glance, it would not seem that the threshold degradation described would be a serious problem until the threshold voltage values of the films reached 5 volts (or whatever the level of the read voltages may be, considering the tolerances involved). However, a memory device having a given initial threshold voltage at room ambient temperature will have a substantially lower initial threshold voltage at substantially higher ambient temperatures, so that, for example, a memory device having an 8 volt threshold voltage at room temperature can have a threshold voltage of 5 volts at ambient temperatures of 100.degree.C. Threshold degradation can thus be especially serious for equipment to be operated, or having specifications ensuring reliable operation, at high ambient temperatures. (It should be noted also that threshold voltages will increase with decrease in ambient temperature so that a memory semiconductor film thickness is limited by the standardized set voltages used in a given system.) In any event, it is apparent that it is important that the memory devices of the memory matrices referred to have a fairly stabilized threshold voltage for a given reference or room temperature, so that the reliability of the matrix can be assured over a very long useful life span under wide temperature ranges like 0.degree.-100.degree.C.
The features of the present invention are particularly useful in memory semiconductor devices utilizing tellurium based chalcogenide glass materials which have the general formula: EQU Ge.sub.A Te.sub.B X.sub.C Y.sub.D
where:
A=5 to 60 atomic percent PA1 B=30 to 95 atomic percent PA1 C=0 to 10 atomic percent when x is antimony (Sb) or Bismuth (Bi) PA1 C=0 to 40 atomic percent when X is arsenic (As) PA1 D=0 to 10 atomic percent when Y is Sulphur (S) PA1 D=0 to 20 atomic percent when Y is Selenium (Se)
or
or
In testing such devices, I discovered that after many tens or hundreds of thousands of set-reset cycles, the threshold voltages level off at plateaus which are proportional to the thickness of the semiconductor film involved. Thus, for example, in the case of the memory material Ge.sub.15 Te.sub.81 Sb.sub.2 S.sub.2, the memory semiconductor film of about 31/2 microns in thickness had a stabilized threshold voltage of between 12 and 13 volts at room ambient temperature and the memory semiconductor film of about 2 microns had a stabilized threshold voltage of near about 8 volts at room ambient temperature. It was postulated that this plateau in the curve of threshold voltage versus number of set-reset cycles for the memory semiconductor devices was the result of an equilibrium between the migration during reset current flow through the previously crystalline filament path (which is mainly crystalline tellurium) of the relatively electronegative tellurium to the positive electrode and the electropositive germanium to the negative electrode and mass transport or diffusion of the same in the opposite direction during and upon the termination of the reset current. The reset current substantially reconverts or dissipates the crystalline tellurium filament into an original amorphous condition of tellurium, germanium and any other elements present in the compositions, although some crystallites of tellurium may remain at widely spaced points of the original filament path. Thus, the electromigration causes the relatively electronegative (e.g. tellurium) to build up a permanently crystalline highly conductive deposit at the positive electrode and the relatively electropositive germanium to build up a relatively conductive deposit at the negative electrode, which deposits are not dissipated at the cessation of reset current flow. This accumulation of tellurium at the positive electrode and germanium at the negative electrode, in effect reduces the thickness of the armorphous high resistance composition of tellurium, germanium and other elements between the accumulation of these deposits. As indicated, the accumulation of these elements at the positive and negative electrodes is opposed after resetting of the memory semiconductor material by diffusion of the materials in the opposite direction to the electromigration to produce a progressively decreasing concentration gradient of these elements. The build up of the tellurium and germanium deposits ceases when equilibrium is reached between electromigration of the elements involved in one direction and diffusion thereof in the opposite direction. The degradation of threshold voltage does not occur when these generally bilateral memory devices are operated with reset pulses which alternate in polarity, because then there is no net migration of the elements involved which tend to build up under the much different D.C. resetting conditions described.
The threshold degradation problem described is one which applied also to memory semiconductor devices having crystalline filaments in their low resistance states and compositions other than those exemplified by the aforesaid formula. However, the above mentioned threshold degradation is not observed in D.C. operated non-memory threshold devices like those described in U.S. Pat. No. 3,271,591, as mechanism devices, where a resetting of the devices is achieved by lowering the current therethrough below a given holding current value. The very modest current conditions during the reading or setting of non-memory threshold devices or memory devices are not believed to cause any significant electromigration. (For example, typical reset currents of memory devices are of the order of magnitude of 150 ma whereas typical read and set currents for these devices and non-memory threshold devices are well under 10 ma.)
The aforementioned short term failure of memory devices where the electrode-semiconductor interface region is damaged is also believed to be a result of the presence of high value reset currents flowing in the under 10 microns width filaments formed in filament-type memory semiconductor devices.